1. Technical Field
The present invention relates generally to a semiconductor memory apparatus, and more particularly to a technology which detects data stored in a memory cell.
2. Related Art
Phase change random access memory (PCRAM) has the characteristics of non-volatility and random accessability, and it can be highly integrated at low cost. PCRAM stores data by using a phase change material that undergoes a phase change at a certain temperature condition, which in turn changes the resistance of the phase change material.
A phase change material can change to an amorphous state or a crystalline state according to a temperature condition. A representative phase change material is a chalcogenide alloy. A representative chalcogenide alloy is Ge2Sb2Te5 composed of germanium (Ge), antimony (Sb), and tellurium (Te). Hence, a phase change material is generally called a “GST”.
A phase change material in a PCRAM undergoes a reversible phase change between a crystalline state and an amorphous state by Joule heating generated when a current or voltage is applied to the phase change material under specific conditions. In circuit terms, a crystalline state is referred to as a set state. In a set state, a phase change material has electrical properties substantially equal to those of a metal having a small resistance value. In circuit terms, an amorphous state is referred to as a reset state. In a reset state, a phase change material has a larger resistance value than that in a set state. That is, a PCRAM stores data through a change in a resistance value between a crystalline state and an amorphous state and determines a level of the stored data by sensing a current flowing through a phase change material or a voltage change depending on a current change. Generally, a set state is defined as a logic level ‘0’, and a reset state is defined as a logic level ‘1’. The set/reset state of a phase change material is continuously maintained even when power is interrupted.
FIG. 1 is a configuration diagram illustrating a memory cell of a conventional PCRAM.
Referring to FIG. 1, a memory cell includes a cell diode D1 and a phase change element GST.
The basic operation of the PCRAM configured as above will be described below.
In particular, an operation of reading data programmed in the phase change element GST is performed as follows.
When a word line WL is enabled to a low level, e.g., a ground voltage, and a read current is transferred through a bit line BL, a cell diode D1 becomes forward biased and turn on after a voltage difference between the anode and cathode of the cell diode D1 is higher than the threshold voltage. A read current path is then formed along the bit line BL, the phase change element GST, and the word line WL, which was enabled to a low level. Therefore, when a predetermined voltage or current is applied to the phase change element GST through the bit line BL, an amount of a current flowing through the phase change element GST or the magnitude of a voltage drop across the phase change element GST is changed depending on the resistance value of the phase change element GST. Using this phenomenon, data stored in the phase change element GST is determined, that is, the state of the phase change element GST is determined.